1. Field of the Invention
The present invention relates to a semiconductor memory device having non-volatile memory cells capable of being electrically programmed and erased. More particularly, this invention is concerned with a NAND-type flash memory having a configuration such that a plurality of non-volatile memory cells are connected in series in units of an information storage region having a given size.
2. Description of the Related Art
In recent years, numerous types of flash memories in which information can be electrically programmed and the whole or part of the information can be electrically erased have been developed as mainstay non-volatile semiconductor memory devices. Above all, a NAND-type flash memory is suitable for a large-capacity file system because &lt;1&gt; although the speed of random access is low, the speed of sequential access is high, &lt;2&gt; writing can be carried out in units of a page, that is, a word line (normally, 264 bytes calculated by adding 8 redundant bytes to 256 bytes or 528 bytes calculated by adding 16 redundant bytes to 512 bytes), &lt;3&gt; that erasure can be carried out in units of a smaller block (normally, 16 pages) compared with a general flash memory referred to as a NOR-type flash memory, &lt;4&gt; that the time required for rewriting data is short, and &lt;5&gt; that since the area of a memory cell is small, a large storage capacity can be attained readily. Markets for this kind of NAND-type flash memory are predicted to expand in the future. The NAND-type flash memory is now attracting attention.
FIG. 1 shows part of the configuration of a memory cell array in a NAND-type flash memory that is an example of a prior art. In the drawing, there are shown word lines WL.sub.1 to WL.sub.16 arranged in units of one block (16 pages), and bit lines BL.sub.1, BL.sub.2, etc. Sixteen non-volatile memory cells (memory cell transistors) (Q1M.sub.1 to Q1M.sub.16 or Q2M.sub.1 to Q2M.sub.16) for storing information are connected in series on each bit line (BL.sub.1 or BL.sub.2) in units of one block, thus constituting one string of memory cells. One terminal of each string of memory cells Q1M.sub.1 to Q1M.sub.16 or Q2M.sub.1 to Q2M.sub.16 is connected with the bit line BL.sub.1, or BL.sub.2 via a selection transistor Q1A.sub.1 or Q2A.sub.1 that responds to the potential on a selection signal line SL.sub.1. The other terminal of each string of memory cells is grounded via a selection transistor Q1A.sub.2 or Q2A.sub.2 that responds to the potential on a selection signal line SL.sub.2.
For storing information in a memory cell, the information is stored as data "1" or data "0." Specifically, data "1" is stored by positively charging the floating gate of the memory cell (that is, by setting the threshold voltage of the memory cell transistor into a negative voltage). Data "0" is stored by negatively charging the floating gate of the memory cell (that is, by setting the threshold voltage of the memory cell transistor to a positive voltage).
For reading information from a memory cell, first, the potentials on the selection signal lines SL.sub.1 and SL.sub.2 are driven high, and the selection transistors Q1A.sub.1, Q2A.sub.1, Q1A.sub.2, and Q2A.sub.2 are all turned on. Consequently, the strings of memory cell Q1M.sub.1 to Q1M.sub.16 and Q2M.sub.1 to Q2M.sub.16 are connected on the bit lines BL.sub.1 and BL.sub.2 and to the ground. Thereafter, 0 V is applied to the control gate of a memory cell from which information should be read (that is, a selected word line), and a high-level voltage is applied to the control gates of the other memory cells (that is, non-selected word lines).
Assuming that information stored in a selected memory cell (=memory cell transistor) is data "1," even when the voltage of the control gate is 0 V, the memory cell transistor is turned on. A cell current flows into an associated bit line. By contrast, assuming that information stored in a selected memory cell is data "0," since the threshold voltage of the memory cell transistor is positive, when the voltage of the control gate is 0 V, the memory cell transistor is turned off. No cell current flows into the bit line. Meanwhile, a high-level voltage is applied to all the control gates of non-selected memory cells. Irrespective of stored information, all the non-selected memory cell transistors are on. A cell current flows into the bit line.
In other words, when information is read, a sense amplifier is used to detect whether or not a selected memory cell causes a cell current to flow into an associated bit line. Thereby, it can be determined whether information stored in the selected memory cell is data "1" or data "0."
As mentioned above, in the NAND-type flash memory, writing or reading is carried out in units of a page (=word line), and erasure is carried out in units of a block (=a plurality of pages). Since a plurality of memory cells are connected in series on each bit line in units of a block, if even one bit location (=one memory cell) within one block or one page is faulty, the operations of memory cells other than the faulty memory cell are affected adversely.
For example, in the configuration shown in FIG. 1, assume that one (Q1M.sub.2) of the 16 memory cells (=memory cell transistors) Q1M.sub.1 to Q1M.sub.16 connected in series on the bit line BL.sub.1 is brought to a non-functional state. In this case, when information is read from the nonfunctional memory cell Q1M.sub.2, since the memory cell transistor is off, no cell current flows into the bit line BL.sub.1. Irrespective of original stored information, data "0" is identified.
When an attempt is made to read information from any of the other memory cells Q1M.sub.1 and Q1M.sub.3 to Q1M.sub.16 contained in the same string of memory cells as the broken memory cell Q1M.sub.2, since the broken memory cell Q1M.sub.2 is off, a current flow is cut off. Even in this case, irrespective of original stored information, data "0" is identified.
A block including a faulty memory cell is a block judged as an unavailable block at the time of delivery of a product, and is, for example, referred to as an "invalid block." After a fault is discovered, access to such an invalid block is inhibited. This is because, as mentioned above, since a NAND-type flash memory is programmed or read in units of a page and erased in units of a block, access to an invalid block involves a string of memory cells in which a fault occurs.
As mentioned above, the NAND-type flash memory has a problem that since the NAND-type flash memory includes strings of memory cell each having a plurality of memory cells connected in series, when one bit location (=one memory cell) in a string of memory cells fails, even if the other memory cells contained in the string of memory cells functions normally, the whole block containing the defective memory cell becomes unavailable. In other words, a majority of normal memory cells other than a minority of defective memory cells (which may be one defective memory cell) among all the memory cells arranged in a limited information storage region are wasted. From the viewpoint of effective utilization of memory cells, there is room for improvement.